Okayama University Faculty of Engineering Dept. of Electrical and Communication Engineering Japanese/English
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In order to design correct asynchronous logic circuits, we study on methods for specification and verification of them. For example, we proposed the followings: Methods for specifying a sequential circuit with N identical modules where N is fixed on application, and for verifying some properties of the circuit which do not depend on N. An efficient method for verifying the validity of state transitions of an asynchronous sequential circuit using the specification and configuration of the circuit. A fast method for timing verification which uses the conditions which cause changes in the output value of gates in a combinational logic circuit. A fast simplex method for deciding whether specified signal changes are occurred or not in an asynchronous circuit.
It is becoming more and more difficult to design high-speed synchronous circuits, in which global clock signals synchronize components, because wire delays are no longer negligibly small in comparison with gate delays. The goal of this study is to develop a systematic method for designing asynchronous processors. We adopt a kind of control-flow graph to represent execution sequences of operations. A given graph is systematically transformed into another graph that enables pipelined execution of operations by the use of dependence relation between them. Generally, such graphs can not be a mapped directly onto asynchronous circuits in which only 0 to 1 transitions are used for events (2-phase circuits) since 1 to 0 transitions are not represented in the graphs. Such a graph must be transformed into another graph (2-phase graph) that can specify 0 to 1 and 1 to 0 transitions simultaneously and can be mapped onto a circuit. Currently, we are tackling a systematic m ethod of such transformation from 1-phase to 2-phase graphs.
We are working on research on error control coding and its applications. The objective for our research is to develop new decoding algorithms for liner block codes and to show the effectiveness of the method by numerical simulations. We are also working on applications of error correcting codes for security purpose.
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